A transistor is designed to be controlled by a relatively small magnitude of voltage but sometimes exposed to undesired high voltage such as, for example, a surge produced from switching operation. This requires a protective network which is expected to decrease the undesired voltage for preventing the transistor from destruction. Many protection networks are evaluated by Jack K. Keller in "PROTECTION OF MOS INTEGRATED CIRCUITS FROM DESTRUCTION BY ELECTROSTATIC DISCHARGE", ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS 1980 , Reliability Analysis Center Sept. 9-11.
Some protective networks are effectively reduced the undesired high voltage and prevents the protected circuits from serious damages. However, when a on-chip protective network is subjected to the undesired high voltage, a high leakage current takes place between the protective network and the semiconductor substrate and deteriorate the power consumption of the protected circuit.
It is therefore a prime object of the present invention to provide an improved protective network which is free from the high leakage current flowing between the protective network and the semiconductor substrate.